module fre_div(
input      clk_in,
output reg clk,
output reg clk_disp
    );
parameter N=25000000;
integer cnt;
 
 
always @(posedge clk_in)
begin                      //ji_shu_fen_pin
   if(cnt == N-1)
   begin
       clk = ~clk;   //ji_shu_fen_pin
       clk_disp=clk;
       cnt = 0;
   end
   else
   begin                      //geng_xin_shi_zhong
       cnt = cnt + 1;
   end
end
endmodule